The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, more specifically a nonvolatile semiconductor memory device including nonvolatile memory cells of the SONOS (Silicon Oxide Nitride Oxide Silicon) structure and a method for fabricating the same.
As rewritable nonvolatile semiconductor memory devices are generally known EEPROM, flash EEPROM, etc., which store charges in the floating gate to thereby memorize information. These nonvolatile semiconductor memory devices, which include control gate functioning as word line and floating gate for memorizing information, require two conducting layers to form the memory cell transistors. On the other hand, as a structure which is simpler and easier to be highly integrated is proposed a nonvolatile semiconductor memory device which uses a dielectric film as the charge storage layer to form the memory cell transistors having single-layer gate.
As the nonvolatile semiconductor memory device having the single-layer gate, the nonvolatile semiconductor memory device of the structure called SONOS (Silicon Oxide Nitride Oxide Silicon) is developed. In the nonvolatile semiconductor memory device using the SONOS technique, e.g., the ONO structure of SiO2/SiN/SiO2 is used as the charge storage layer, and charges are retained in the defects in the SiN to thereby memorize information. For higher integration and further cost reduction, a 2-bit operative nonvolatile semiconductor memory device which can retain charges locally in the source ends and the drain ends is developed.
Such 2-bit operative nonvolatile semiconductor memory device has a merit that with the same cell numbers, the storage memory number is simply twice and a merit that with the same storage memory numbers, the chip area can be simply reduced in half, and is a very prospective device which can simultaneously satisfy the requirements of high integration and cost reduction.
The nonvolatile semiconductor memory device using the SONOS technique is described in, e.g., Reference 1 (U.S. Pat. No. 5,966,603), Reference 2 (U.S. Pat. No. 6,215,148), Reference 3 (U.S. Pat. No. 6,297,096), Reference 4 (U.S. Pat. No. 6,468,865), Reference 5 (U.S. Pat. No. 6,541,816), and Reference 6 (Japanese published unexamined patent application No. 2002-541665).
In the nonvolatile semiconductor memory device described in References 1 to 3, after the charge retaining insulating film (ONO film) is grown, the bit lines in the memory cell array are patterned by using a mask of photoresist or others, and after the ON film which is the upper part of the charge retaining insulating film is etched, ion implantation for the bit lines is performed. In the nonvolatile semiconductor memory device described in Reference 2, after these steps, with the same mask, pocket ion implantation is performed, and then after the mask is removed the bit line oxidation film is grown, and a polycrystalline silicon film, etc. to be the word lines is grown.
In the nonvolatile semiconductor memory device described in Reference 4, after the charge retaining insulating film is grown, the bit lines in the memory cell array are patterned with a mask of photoresist film or others, and then after the ion implantation for the bit lines is performed, the charge retaining insulating film on the bit lines is removed, the bit line oxidation film is formed, and a polycrystalline silicon film, etc. to be the word lines is grown.
In the nonvolatile semiconductor memory device described in Patent Reference 5, after the charge retaining insulating film is grown, the bit lines in the memory cell array are patterned with a mask of photoresist film or others, and then after ion implantation for the bit lines is performed, a polycrystalline silicon film, etc. to be the word lines is grown.